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| author | root <root@turin.home> | 2022-02-27 13:04:04 +0000 |
|---|---|---|
| committer | root <root@turin.home> | 2022-03-07 11:35:34 +0000 |
| commit | 3d5309ad02ca220f0cd3055af7e4287841415c79 (patch) | |
| tree | 296368f581b398ff64095ed45f7a123e2ac48895 /refer | |
| parent | d915196f3c57d86e47675035aafbf82216efe745 (diff) | |
Changes is intro, doing todos/citations
Diffstat (limited to 'refer')
| -rw-r--r-- | refer | 14 |
1 files changed, 14 insertions, 0 deletions
@@ -247,3 +247,17 @@ %J Karlstad University %G arXiv:1204.0447 [cs.CR] %D Apr 2012 + +%A Chen Chen^et^al +%T Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension +%D 2020 +%J ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA) +%O DOI: 10.1109/isca45697.2020.00016 + +%T Instruction Sets Should Be Free: The Case For RISC-V +%A Krste Asanović +%A David A. Patterson +%J Electrical Engineering and Computer Sciences +%C University of California at Berkeley +%R UCB/EECS-2014-146 +%D Aug 2014 |